IEE5049: Digital Integrated Circuits

數位積體電路

Institute of Electronics, National Chiao-Tung University
Spring 2012

 


<Course Informations>

- Instructor -

- Course Focus and Objective -

  • CMOS Transistor and Technology - Scaling and Its Limits
  • Interconnect, Delay, Power, and Robustness
  • Circuit Simulation, Combinational and Sequential Circuit Design
  • Data path and Array Subsystems
  • Special - Purpose Subsystem
  • Low Power VLSI Design
  • Timing and Variability - award VLSI design
  • Degisn Methodology amd Tools
  • Testing, Debugging and Verification
  • Learn the fundamental of digital VLSI circuits and sustems design
  • Gain basic understanding of system design methodology
  • Become familiar with advanced IC/SoC/SiP industry and research trends

- Text Books -

  • Weste/Harris, "CMOS VLSI Design", 4th, Addison Weley,2011
  • Rebaey, "Low Power Design Essentials", Spring, 2009
  • Harris/Harris, "Digital Deaign and Computer Architecture", Elsevier, 2007
  • Rabaey et al, "Digital Integrated Circuits", Prentice Hall, 2003

- Regular Class Hours -

  • Thu. EFG, 1:30-4:30 pm (電資大樓MIRC R201)

- Teaching Assistant -

- Assistant -


<Course Announcements>

- Announcement -

  • First lecture will be on Feb. 23.
  • The classroom is changed to MIRC 電資大樓 R201.
  • HSPICE Tutorial is revised. Please download the latest version.

- Lectures -

- Supplemental Reading Materials -

- Term Project -

- Exercise -

- Oral Presentaion Subject -