2014

    Journal Papers
    1. Nan-Chun Lien, Li-Wei Chu , Chien-Hen Chen , Hao-I Yang , Ming-Hsien Tu , Paul-Sen Kan , Yong-Jyun Hu , Ching-Te Chuang , Shyh-Jye Jou , Wei Hwang, "A 40nm 512Kb Cross-Point 8T Pipeline SRAM with Binary Word-Line Boosting Control, Ripple Bit-Line and Adaptive Data-Aware Write-Assist," IEEE Transitions on Circuits and Systems I (TCASI) Vol. 61, No.12-, pp. 3416-3425, December 2014 .
    2. Lei-Chun Chou, Chih-Wei Chang, Po-Tsang Huang, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuan-Neng Chen, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsang Chiu, and Ho-Ming Tong "A New Fabrication Process for TSV-based Bio-Signal Packaging," Storage Management Solutions, pp. 157-168, Issues 3, May 2014.
    3. Yu-San Chien, Yan-Pin Huang, Ruoh-Ning Tzeng, Ming-Shaw Shy, Teu-Hua Lin, Kou-Hua Chen, Chi-Tsung Chiu, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ho-Ming Tong, and Kuan-Neng Chen, "Low-Temperature Bonded Cu/In Interconnect with High Thermal Stability for 3-D Integration," IEEE Transactions on Electron Devices, 61(4), pp. 1131-1136, April. 2014
    4. Dao-Ping Wang, Hon-Jarn Lin, Ching-Te Chuang, and Wei Hwang*, "Low Power Multi-Port SRAM with Cross-Point Write World-Line, Shared Write Bit-Line and Shared Write Row-Access Transistors," IEEE Transitions on Circuits and Systems II: Express Briefs, Vol. 61, No 3, pp. 182-192, March 2014.
    5. Lei-Chun Chou, Shih-Wei Lee, Po-Tsang, Chih-Wei Chang, Cheng-Hao Chiang, Shang-Lin Wu, Ching-Te Chuang, Jin-Chern Chiou, Wei Hwang, Chuang-His Wu, Kuo-Huao Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Kuan-Neng Chen, "A TSV-Based Bio-Signal Package with u-probe Array," IEEE Electron Device Letters, Vol.35, No.2, pp.256-258, Feb. 2014.
    Conference Papers

    1. Po-Tsang Huang, Shu-Lin Lai, Ching-Te Chuang, Wei Hwang, Jason Huang, Angelo Hu, Paul Kan, Michael Jia, Kimi Lv and Bright Zhang, "0.339fJ/bit/search Energy-Efficient TCAM Macro Design in 40nm LP CMOS," 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC 2014),pp. 129-132, KaoHsiung, Taian, November 10-12, 2014 .
    2. Sang H. Dhong and Wei Hwang, "Recent Advances in ASIC-Compatible Circuit Techniques for a SOC in emerging new application areas," 11th International SoC Design Conference (ISOCC2014), Jeju, Korea, Nov. 3-6, 2014 .
    3. Ming-Zhang Kuo, Herny Hsieh, Sang Dhong, Ping-Lin Yang, Cheng-Chang Lin, Ryan Tseng Kevin Huang, Ming-Jer Wang and Wei Hwang, "A 16KB Tile-able SRAM Macro Prototype for an Operating Window of 4.8GHzat 1.12V VDD to 10MHz t 0.5 V in a 28-nm HKMG CMOS," The IEEE Custom Integrated Circuits Conference (CICC 2014), Ses. 21-2 , San Jose, CA, USA, September 15-17, 2014 .
    4. Sang Dhong, Richard Guo, Ming-Zhang Kuo, Ping-Lin Yang, Cheng-Chung Lin, Kevin Huang, Min-Jer Wang and Wei Hwang, "A 0.42V Vccmin ASIC-Compatible Pulse-Latch Solution as a Replacement for a Traditional Master-Slave Flip-Flop in a Digital SoC," The IEEE Custom Integrated Circuits Conference (CICC 2014), Sec. 05-3 , San Jose, CA, USA, September 15-17, 2014 .
    5. Po-Tsang Huang, Yu-Rou Lin, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsung Chiu, Sog Yang and Ho-Ming Tong, "μ-SPI: A Low Power On-Interposer Bus for 2.5D Heterogeneously Integrated Biomedical Microsystems," The 25th VLSI Design/CAD 2014, Taichung, Taiwan Aug. 2014 .
    6. Chih-Yuan Chang, Po-Tsang Huang, Yi-Chun Chen, Tian-Sheuan Chang and Wei Hwang, "Thermal-Aware Memory Management Unit of 3D Stacked DRAM for 3D High Definition (HD) Video," IEEE International SoC Conference (SOCC 2014), Proceedings, pp. 122-127, Las Vegas, Nevada, USA, September 2-5, 2014 .
    7. Pei-Chen Wu, Yi-Ping Kuo, Chung-Shiang Wu, Ching-Te Chuang, Yuan-Hua Chu and Wei Hwang, "PVT- Aware Digital Controlled Voltage Regulator Design for Ultra-Low-Power (ULP) DVFS Systems," IEEE International SoC Conference (SOCC 2014), Proceedings, pp. 182-185, Las Vegas, Nevada, USA, September 2-5, 2014 .
    8. Tang-Hsuan Wang, Po-Tsang Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang and Wei Hwang , "Energy-Efficient Configurable Discrete Wavelet Transform for Neural Sensing Application," 2014 IEEE International Symposium on Circuits and Systems, (ISCAS 2014), pp. 1841-1844, Melbourne, Australia, June 1-5, 2014 .
    9. Lei-Chun Chou, Shih-Wei Lee, Po-Tsang Huang, Chih-Wei Chang, Shang-Lin Wu, Ching-Te Chuang, Jin-Chern Chiou, Wei Hwang, Chung_Hsi Wu, Kuo-Hua Chen, Chi-Tsang Chiu, Ho-Ming Tong and Kuan-Neng Chen, "Integrated Microprobe Array and CMOS MEMS by TSV Technology for Bio-Signal Recording Applications," Proceedings of ECTC 2014, pp. 512-517, Lake Buena Vista, Fl., USA, May 27-30, 2014.
    10. Shang-Lin Wu, Po-Tsang Huang, Teng-Chieh Huang, Kuan-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Ching-Te Chuang and Wei Hwang, "Energy-Efficient Low-Noise 16-Channel Analog Front-End Circuit for Bio-potential Acquisition," 2014 IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Proceedings of Technical Papers. pp. 117-120, Hsinchu, Taiwan, April 28-30, 2014.
    11. Lei-Chun Chou, Shih-Wei Lee, Po-Tsang Huang, Chih-Wei Chang, Cheng-Hao Chiang, Shang-Lin Wu, Ching-Te Chuang, Jin-Chern Chiou, Wei Hwang, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, Kuan-Neng Chen, "A TSV-Based Heterogeneous Integrated Neural-Signal Recording Device with Microprobe Array," 2014 IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Proceedings of Technical Papers. pp. 149-150, Hsinchu, Taiwan, April 28-30, 2014.
    12. Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Teng-Chieh Huang, Tang-Shuan Wang, Yu-Ron Lin, Chuan-An Cheng, Kuan-Neng Chen, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Kuo-Hua Chen, Chi-Tsuang Chiu , Ming-Hsiang Cheng, Yueh-Lung and Ho-Ming Tong, "2.5 D Heterogeneously Integrated Bio-Sensing Microsystem for Multi-Channel Neural Sensing Applications," 2014 IEEE International Solid-State Circuits Conference (ISSCC), Technical Digester, pp. 320-321, San Francisco, CA, February 9-13, 2014.

     

    United States Patents Granted
    1. Wei Hwang and and Dao-Ping Wang, "Ten-Transistor Dual-Port SRAM with Shared Bit-line Architectures," US Patent No.8,891,289 B2, November 18, 2014.
    2. Ching-Te Chuang, Nan-Chun Lien, Wei-Nan Liao, Chi-Hsin Chang, Hao-I Yang, Wei Hwang, and , Ming-Hsien Tu, "Static Random Access Memory Apparatus and Bit-line Voltage Controller Thereof," US Patent No. 8,854,897 B2, Oct. 7, 2014.
    3. Ching-Te Chuang, ShyhJye Jou, Wei Hwang, Ming-Chien Tsai, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shieh, Nan-Chun Lien and Kuen-Di Lee, "Oscillator Based on 6T SRAM for Measuring the Bias Temperature Instability," U.S. Patents 8,804,445 B2, Aug. 12, 2014
    4. Ching-Te Chuang, Hao-I Yang, Chien-Yu Lu, Chien_Hen Chen, Chi-Shing Han, Po-Tsang Huang, Shu-Lin Lai, Wei Hwang, Shyh-Jye Jou and Ming-Hsieh Tu, "Static Random Access Memory with Ripple Bitlines/Search lines for Improving current Leakage/Variation Tolerance and Density/Performance," U.S. Patents 8,773,894 B2, July 08, 2014.
    5. Ching-Te Chuang, Hao- Yang, Mao-Chih Hsia, Wei Hwang, Chia-Cheng Chen and Wei-Chiang Shih, " Low Power Static Random Access Memory," U.S. Patents 8,695,936 B2, Feb. 25, 2014.

     

    Taiwan Patents Granted
    1. 楊仕祺、楊皓義、黃威, “次臨界多埠暫存器”, 中華民國專利證書 (TW I453749), September 21, 2014.
    2. 謝維致及黃威,“數位式線性電壓調整器”,中華民國專利證書 (TW I449318),August 11, 2014.
    3. 楊浩義,莊景德及黃威, “可容忍閘極崩毀之功率閘結構”, 中華民國專利證書, (TW I443807), July 1, 2014.
    4. 陳璽文, 、張銘宏、謝維致, 黃威, “全晶上寬工作電壓溫度製程電壓感測器”, 中華民國專利證書 (TW I422847), January 11, 2014.

2013

    Journal Papers
    1. Pan-Pin Huang, Yu-San Chien, Ruoh-Ning Tseng, Ming-Shaw Shy, Teu-Hua Lin, Kou-Hua Chen, Chi-Tsung Chiu, Jin-Chern Chiou, Ching-Te Chuang, Wei Hwang, Ho-Ming Tong, and Kuan-Neng Chen, "Novel Cu-to-Cu Bonding with Ti Passivation at 180 °C in 3-D Integration," IEEE Electron Device Letters, 34(12), pp. 1551-553, Dec. 2013.
    2. Dao-Ping Wang, Hon-Jarn Lin, and Wei Hwang, "A Two-Write and Two-Read Multi-Port SRAM with Shared Write Bit-Line Scheme and Selective Read Path for Low Power Operation," ASP Journal of Low Power Electronics, Vol 9, No. 1, pp. 9-22, April 2013.
    Conference Papers

    1. Teng-Chieh Huang, Po-Tsang Huang, Shang-Lin Wu, Kung-Neng Chen, Jin-Chern Chiou, Kuo-Hua Chen, Chi-Tsung Chiou, Ho-Ming Tong, Ching-Te Chuang, and Wei Hwang, "Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanced Tuning for Neural Sensing Applications," IEEE Biomedical Circuits and Systems Conference, Rottendam, The Netherland. Oct. 31-Nov., 2013
    2. Y. P. Huang, Y. S. Chien, R. N. Tzeng, M. S. Shy, T. H. Lin, K. H. Chen, C. T. Chuang, Wei Hwang, C. T. Chiu, H. M. Tong, and K. N. Chen, "Low Temperature (<180°C) Bonding for 3D Integration," IEEE 3D System Integration Conference, San Francisco, CA, USA, Oct. 2-4, 2013.
    3. Mei-Wei Chen, Ming-Hung Chang, Pei-Chen Wu, Yi-Ping Kuo, Chun-Lin Yang, Yuan-Hua Chu and Wei Hwang , "A PVT Robust Dual-Edged Triggered Explicit-Pulsed Level Converting Flip-Flop with a Wide Operation Range," 26Th IEEE International SoC Conference (SOCC), September 04-06, 2013.
    4. Wei-Nan Liao, Nan-Chun Lien, Chi-Shin Chang, Li-Wei Chu, Hao-I Yang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Ming-Hsien Tu, Huan-Shun Huang, Jian-Hao Wang, Paul-Sen Kan and Yong-Jyun Hu, "A 40nm 1.0Mb 6T Pipeline SRAM with Digital-Based Bit-Line Under-Drive, Three-Step-Up Word-Line, Adaptive Data-Aware Write-Assist with VCS Tracking and Adaptive Voltage Detector for Boosting Control," 26Th IEEE International SoC Conference (SOCC), September 04-06, 2013.
    5. Ruoh- Ning Tzeng, Yen-Pin Huang, Yu-San Chien, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ming-Shaw Shy, Teu-Hua Lin, Kou-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Kuan-Neng Chen, "Low Temperature Bonding of Sn/In-Cu Interconnects for Three-Dimensional Integration Applications," 2013 IEEE International Interconnect Technology Conference (IITC), Jun 13-15, 2013.
    6. Ming-Hung Chang, Wei- Chih Hsieh, Pei-Chen Wu, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kua-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Wei Hwang, "Multi-Layer Adaptive Power Management Architecture for TSV 3-D IC Technology," ECTC 2013, pp. 1179-1185, Las Vegas, May 28-31, 2013.
    7. Ming-Hung Chang, Shang-Yuan Lin, Pei-Chen Wu, Ching-Te Chuang, Kuan-Neng Chen, Chen-Chao Wang, Kua-Hua Chen, Chi-Tsung Chiu, Ho-Ming Tong, and Wei Hwang, "Near-/Sub-Vth Process, Voltage, and Temperature (PVT) Sensors with Dynamic Voltage Selection," , 2013 IEEE International Symposium on Circuits and Systems ( ISCAS 2013), pp. 133-136, Beijing, China, May 19-23, 2013.
    8. Chi-Shin Chang, Hao-I Yang, Wei-Nan Liao, Yi-Wei Lin, Nan-Chun Lien, Chien –Hen Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun huang, Yong-Jyun Hu, Paul-Sen Kan, Cheng-Yo Cheng, Wei-Chang Wang, Jia-Cheng Chen, Kuen-Di Lee, Chia-Cheng Chen and Wei-Chiang Shih, "A 40nm 1.0Mb Pipeline 6T SRAM with Variation-Tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist," 2013 IEEE International Symposium on Circuits and Systems (ISCAS 2013), pp. 1466-1471, Beijing, China, May 19-23, 2013.
    9. Y. S. Chien, Y. P. Huang, R. N. Tzeng, M. S. Shy, T. H. Lin, K. H. Chen, C. T. Chuang, Wei Hwang, C. T. Chiu, H. M. Tong, and K. N. Chen, "Low Temperature (<180C) Wafer-level and Chip-level In-to-Cu and Cu-to-Cu Bonding for 3D Integration," ECTC 2013, pp. 1146-1152, Las Vegas, May 28-31, 2013.
    10. Shih- Wei Lee, Yu-Chen Hu, Cheng-Hao Chiang, Kuo-Hua Chen, Chi-Tsung Chiu, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ho-Ming Tong, and Kuan-Neng Chen, "Integration, Electrical Performance and Reliability Investigation of TSV" IMAPS 9th International Conference and Exhibition on Device Packaging, Scottsdale, AZ, USA, March 12-14, 2013.
    11. Chih-Wei Chang, Po-Tsang Huang, Lei-Chun Chou, Shang-Lin Wu, Shih-Wei Lee, Ching-Te Chuang, Kuan-Neng Chen, Jin-Chern Chiou, Wei Hwang, Yen-Chi Lee, Chung-Hsi Wu, Kuo-Hua Chen, Chi-Tsung Chiu, and Ho-Ming Tong, "Through-Silicon-Via Based Double-Side Integrated Microsystem for Neural Sensing Applications," 2013 IEEE International Solid-State Circuits Conference (ISSCC), pp.102-103, San Francisco, CA, February 17-21,2013.

     

    United States Patents Granted
    1. Chi-Te Chiu, Ming-Hung Chang, Hao-Yi Yang and Wei Hwang, "Dual-Port Subthresold SRAM Cell," U.S. Patents 8,498,174 B2, July 30, 2013.
    2. Chuang- Ying Hsieh, Ming-Hung Chang and Wei Hwang, "Method for buffering clock skew by using a logical effort," U.S. Patents 8,487,684, July 16, 2013
    3. Chi-Te Chiu, Ming-Hung Chang, Hao-Yi Yang and Wei Hwang, "Static Random Access Memory Cell and Method of Operation the Same," U.S. Patents 8,437,178 B2, May 7, 2013
    4. Tien-Hung Lin, Po-Tsang Huang and Wei Hwang, "On-Chip Active Decoupling Capacitors for Regulating Voltage of Integrated Circuits," U.S. Patents 8,427,224 B2, April 23, 2013.
    5. Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, and Wei Hwang, " Fully-on-Chip Temperature, Process , Voltage Sensor Systems," U.S. Patents 8,419,274 B2, April 16, 2013
    6. Hao-I Yang, Ching-Te Chuang and Wei Hwang,"Gateo xide Breakdown-Withstanding Power Structure," U.S. Patent 8,385,149, Feb. 26, 2013.
    7. Ching-Te Chung, Hao-I Yang, Yi-Wei Lin, Wei Hwang, Wei_Chiang Shih, and Chia-Cheng Chen, "Data-Aware Dynamic Supply Random Access Memory," U.S. Patent 8,345,504, Jan. 01, 2013.

     

    Taiwan Patents Granted
    1. 楊仕祺, 楊浩義,莊景德及黃威,”靜態隨機存取記憶體裝置”, 中華民國專利證書, (TW I419173), December 11, 2013.
    2. 張牧天、黃柏蒼及黃威,”靜態隨機存取記憶體裝置”, 中華民國專利證書, (TW I419160), December 11, 2013.
    3. 蔡同豪,謝維致,黃威, “太陽能電源管理裝置及其管理方法”, 中華民國專利證書, (TW I407662),September 1, 2013

2012

    Journal Papers
    1. Chien-Yu Lu, Ming-Hsien Tu, Hao-I Yang, Ya-Ping Wu, Huan-Shun Huang, Yuh-Jiun Lin, Kuen-Di Lee, Yung-Shin Kao, Ching-Te Chuang, , Shyh-Jye Jou, and Wei Hwang, "A 0.33V, 500KHz, 3.94μW 40nm 72Kb 9T Subthreshold SRAM with Ripple Bit-Line Structure and Negative Bit-Line Write-Assist," IEEE Transitions on Circuits and Systems II: Express Breiefs, Vol. 58, No.12, pp. 863-867, pp.863-867, December 2012.
    2. Dao-Ping Wang and Wei Hwang, "A 45nm 10T Dual-Port SRAM with Shared Bit-Line Scheme for Low Power Operation," Journal of Low Power Electronics, Vol. 8, No. 4, pp. 472-484, August 2012.
    3. Ming-Hung Chang, Yi-Te Chiu, and Wei Hwang, "Design and iso-area Vmin analysis of 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS," IEEE Transactions on Circuits and Systems II: Express Brief, vol. 59, no. 7, pp.429-433, Jul. 2012.
    4. Wei-Chih Hsieh and Wei Hwang, "All digital linear voltage regulator for super- to near-threshold operation," IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 20, no. 6, pp. 989-1001, Jun. 2012.
    5. Ming-Hung Chang, Shang-Yuan Lin, and Wei Hwang, "A 0.4V 520nW 990um2 fully integrated frequency-domain temperature sensor in 65nm CMOS," Journal of Low Power Electronics, vol. 8, no. 1, Feb. 2012, pp. 63-72, February 2012.
    6. Po-Tsang Huang and Wei Hwang, "Self-calibrated energy-efficient and reliable channels for on-chip interconnection networks," Journal of Electrical and Computing Engineering, 2012.
    Conference Papers

    1. Y. P. Huang, R. N. Tzeng, Y. S. Chien, M. S. Shy, H. S. Chang, T. H. Lin, K. H. Chen, C. T. Chiu, Y. E. Yeh, Wei Hwang, C. T. Chuang, J. C. Chiou, H. M. Tong, K. N. Chen, "Low Temperature Cu-Sn and Sn-Sn Bonding Development for 3D Interconnect Applications," International Electron Devices and Materials Symposium 2012,Kaohsiung, Taiwan, Nov 29-30, 2012.
    2. [65] Y. C. Hu, C. H. Chiang, K. H. Chen, C. T. Chiu, C. T. Chuang, W. Hwang, J. C. Chiou, H. M. Tong, K. N. Chen, "Micro-masking Removal of TSV and Cavity during ICP Etching Using Parameter Control in 3D and MEMS Integrations," The 7th IMPACT 2012 Conference, Taipei, Taiwan, Oct 24-26, 2012.
    3. Yu-Chen Hu, Cheng-Hao Chiang, Kuo-Hua Chen, Chi-Tsung Chiu, Ching-Te Chuang, Wei Hwang, Jin-Chern Chiou, Ho-Ming Tong, and Kuan-Neng Chen, "Study of TSV Formation with ICP Parameter Control," The 34th International Symposium on Dry Process,pp. 127-128, Tokyo, Japan, Nov 15-16, 2012.
    4. C. H. Chiang, Y. C. Hu, K. H. Chen, C. T. Chiu, C. T. Chuang, W. Hwang, J. C. Chiou, H. M. Tong, K. N. Chen, "Investigation of ICP Parameters for Smooth TSVs and Following Cu Plating Process in 3D Integration," The 7th IMPACT 2012 Conference, pp. 367-369,Taipei, Taiwan, Oct 24-26, 2012.
    5. Tsu-Ting Chiang, Po-Tsang Huang, C.-T. Chuang, J-C Chiou, K.-N. Chen, K.-H. Chen, C.-T. Chiu, H.-M. Tong, and Wei Hwang, "On Chip Self-Calibrated Process-Temperature Sensor for TSV 3D Integration," 2012 IEEE International SoC Conference (SOCC), Niagara Falls, NY, USA, Sept. 12 -14, 2012.
    6. Mei-Wei Chen, Ming-Huang Chang,Yuan-Hwa Chu and Wei Hwang, "An Energy-Efficient Level Converter with High Thermal Variation Immunity for Sub-threshold to Super-thresold Operation," 2012 IEEE International SoC Conference (SOCC), Niagara Falls, NY, USA, Sept. 12 -14, 2012.
    7. Yung-Wei Lin, Hao-I Yang, Mao-Chih Hsia, Yi-Wei Lin, Chien-Hen Chen, Ching-Te Chuang, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee and Chih-Chiang Hsu, "A 55nm 0.5V 128Kb Cross-Point 8T SRAM with Data-Aware Dynamic Supply Write-Assist," 2012 IEEE International SoC Conference (SOCC), Niagara Falls, NY, USA, Sept. 12 -14, 2012.
    8. P-T. Huang, T.-T. Chiang, H. Chiueh, C.-T. Chuang, J-C Chiou, K.-N. Chen, K.-H. Chen, C.-T. Chiu, H.-M. Tong, and W. Hwang, "Thermal Management with In-Situ Process-Temperature Sensor for TSV 3D-ICs," 2012 VLSI-CAD Symposium.
    9. P-T Huang, Yung Chang, Shiang-Fei Wang and Wei Hwang, "An Efficient Network Interface for Memory-Centric On-Chip Interconnection Network," 2012 VLSI-CAD Symposium.
    10. Yi-Wei Lin, Hao-I Yang, Geng-Cing Lin, Chi-Shin Chang, Ching-Te Chuang, Wei Hwang, Chia-Cheng Chen, Willis Shih, Huan-Shun Huang, "A 55nm 0.55V 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist," IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Jul. 2012.
    11. Po-Jen Yang, Po-Tsang Huang and Wei Hwang, "Substrate noise suppression technique for power integrity of TSV 3D integration," IEEE Int. Symp. Circuits and Systems (ISCAS), May 2012.
    12. Hao-I Yang, Yi-Wei Lin, Mao-Chih Hsia, Geng-Cing Lin, Chi-Shin Chang, Yin-Nien Chen ,Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, and Chih-Chiang Hsu, "High performance 0.6V Vmin 55nm 1.0Mb 6T SRAM with adaptive BL bleeder," IEEE Int. Symp. Circuits and Systems (ISCAS), May 2012.
    13. Ming-Chien Tsai, Yi-Wei Lin, Hao-I Yang, Ming-Hsien Tu, Wei-Chiang Shih, Nan-Chun Lien, Kunti Lee, Shyh-Jye Jou, Ching-Te Chuang, and Wei Hwang, "Embedded SRAM ring oscillator for in-situ measurement of NBTI and PBTI degradation in CMOS 6T SRAM array," Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2012.
    14. Wei-Hung Du, Po-Tsang Huang, Ming-Hung Chang, and Wei Hwang, "A 2kb built-in row-controlled dynamic voltage scaling near-/sub-threshold FIFO memory for WBANs," Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2012.
    15. Yi-Wei Lin, Ming-Chien Tsai, Hao-I Yang, Geng-Cing Lin, Shao-Cheng Wang, Ching-Te Chuang, Shyh-Jye Jou, Wei Hwang, Nan-Chun Lien, Kuen-Di Lee and Wei-Chiang Shih, "An all-digital read stability and write margin characterization scheme for CMOS 6T SRAM array," Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2012.

     

    United States Patents Granted
    1. Ching-Te Chung, Hao-I Yang,Mao-Chih Hsia, Yung-Wei Lin, Chien-Yu Lu, Ming-Hsien Tu, Wei Hwang, Shyh-Jye Jou, Chia-Cheng Chen, and Wei_Chiang Shih, "Static Random Access Memory With Data Controlled Power Supply," U.S. Patent 8,320,164, Nov. 27, 2012.
    2. Ching-Te Chung, Hao-I Yang, Jihi-Yu Lin, Shyh-Chyi Yang Ming-Hsien Tu, Wei Hwang, Shyh-Jye Jou, Kun-Ti Lee and Hung-Yu Li, "Disturb-Free Static Random Access Memory Cell," U.S. Patent 8,259,510, Sep. 4, 2012.
    3. Chun-Yi Wu, Wei-chi Hsieh and Wei Hwang, "Solar Power Management System," U.S. Patent 8,258,741, Sep. 4, 2012.
    4. Chung-Ying Hsieh, Ming-Hung Chang and Wei Hwang, "Programble Clock Generator Used in Dynamic-Voltage-and-Frequency Scaling (DVFS) Operated in Sub- and Near-Threashold Region," U.S. Patent 8,237,477, Aug. 7, 2012.
    5. Wei-chi Hsieh and Wei Hwang, "Self-Aware Adapative Power Control System and A Method for Determining the Circuit State," U.S. Patent 8,138,795, Mar. 20, 2012.
    6. Chun-Yi Wu, Wei-Chi Hsieh, Ming-Hung Chang and Wei Hwang, "Charge Pump," U.S. Patent 8,125,263, Feb. 28, 2012.

     

    Taiwan Patents Granted
    1. 楊仕祺, 楊浩義,莊景德及黃威,”靜態隨機存取記憶體裝置”, 中華民國專利證書, (TW I419173), December 11, 2013.
    2. 張牧天、黃柏蒼及黃威,”靜態隨機存取記憶體裝置”, 中華民國專利證書, (TW I419160), December 11, 2013.
    3. 蔡同豪,謝維致,黃威, “太陽能電源管理裝置及其管理方法”, 中華民國專利證書, (TW I407662),September 1, 2013

2011

    Journal Papers
    1. Po-Tsang Huang and Wei Hwang, "Two-level FIFO buffer design for routers in network-on-chip platform," IEICE Transactions on Fundamentals of Electronics, Communications, and Computer Sciences, vol. E94-A, no. 11, Nov. 2011, pp. 2412-2424.
    2. Hao-I Yang, Wei Hwang, and Ching-Te Chuang, "Impacts of NBTI/PBTI and contact resistance on power-gated SRAM with high-κ metal-gate devices," IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 7, Jul. 2011, pp. 1192-1204.
    3. Wei-Chih Hsieh and Wei Hwang, "Adaptive power control technique on power-gated circuitries," IEEE Transaction on Very Large Scale Integration (VLSI) Systems, vol. 19, no. 7, Jul. 2011, pp. 1167-1180.
    4. Hao-I Yang, Shyh-Chyi Yang, Wei Hwang, and Ching-Te Chuang, "Impacts of NBTI/PBTI on timing control circuits and degradation tolerant design in nanoscale CMOS SRAM," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 58, no. 6, Jun. 2011, pp. 1239-1251.
    5. Po-Tsang Huang and Wei Hwang, "A 65 nm 0.165 fJ/Bit/Search 256x144 TCAMMacro Design for IPv6 Lookup Tables," IEEE Journal of Solid-State Circuits, vol. 46, no. 2, Feb. 2011, pp. 507-519.
    6. Hao-I Yang, Wei Hwang, and Ching-Te Chuang, "Impacts of gate-oxide breakdown on power-gated SRAM," Microelectronics Journal, vol. 43, Jan. 2011, pp. 101-112.
    Conference Papers

    1. Wei Hwang, "3D SiP: Prospects and Challenges," (invited paper), 3-D Architectures for Semiconductor Integration and Packaging Conference, Dec. 2011.
    2. Po-Tsang Huang, Tzu-Ting Chiang, Herming Chiueh and Wei Hwang, "Thermal Control Mechanism with In-Situ Temperature Sensor for TSV 3D-ICs," IEEE International Workshop on Thermal Investigations of ICs and Systems (Thermnic), Sep. 2011, pp. 189-194.
    3. Wei-Hung Du, Ming-Hung Chang, Hao-I Yang, and Wei Hwang, "An energy-efficient 10T SRAM based FIFO memory operating in near-/sub-threshold regions," IEEE Int. SoC Conf. (SOCC), Sep. 2011, pp. 19-23.
    4. Hao-I Yang, Shih-Chi Yang, Mao-Chih Hsia, Yung-Wei Lin, Yi-Wei Lin, Chien-Hen Chen, Chi-Shin Chang, Geng-Cing Lin, Yin-Nien Chen, Ching-Te Chuang, Wei Hwang, Shyh-Jye Jou, Nan-Chun Lien, Hung-Yu Li, Kuen-Di Lee, Wei-Chiang Shih, Ya-Ping Wu, Wen-Ta Lee, and Chih-Chiang Hsu "A high-performance low Vmin 55nm 512kb disturb-free 8T SRAM with adaptive VVSS control," IEEE Int. SoC Conf. (SOCC), Sep. 2011, pp. 197-200.
    5. Po-Tsang Huang, Yung Chang, and Wei Hwang, "On-demand memory sub-system for multi-core SoCs," IEEE Int. SoC Conf. (SOCC), Sep. 2011, pp. 122-127.
    6. Ming-Hung Chang, Yi-Te Chiu, Shu-Lin Lai, and Wei Hwang, "A 1kb 9T subthreshold SRAM with bit-interleaving scheme in 65nm CMOS," IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2011, pp. 291-296.
    7. Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, and Wei Hwang, "Near-/sub-threshold DLL-based clock generator with PVT-aware locking range compensation technique," IEEE Int. Symp. Low Power Electronics and Design (ISLPED), Aug. 2011, pp. 15-20.
    8. Ming-Hung Chang, Chung-Ying Hsieh, Mei-Wei Chen, and Wei Hwang, "Logical effort models with voltage and temperature extensions in super-/near-/sub-threshold regions," Int. Symp. VLSI Design, Automation, and Test (VLSI-DAT), Apr. 2011, pp. 1-4.

     

    United States Patents Granted
    1. Mu-Tien Chang, Po-Tsang Huang, Wei Hwang, "Dual-Threshold-Voltage Two-Port Sub-Threshold SRAM Cell Apparatus," U.S. Patent 8,072,818, Dec. 6, 2011.
    2. Po-Tsang Huang, Shu-Wei Chang, and Wei Hwang, "Butterfly match-line structure and method implemented thereby," U.S. Patent 7,903,443, Mar. 8, 2011.

     

    Taiwan Patents Granted
    1. Po-Tsang Huang, Wen-Yen Liu and Wei Hwang, "三元內容可定址記憶體漏電流截斷裝置," TW Patent I3492943, Oct. 1, 2011.
    2. Wei-Chih Hsieh ane Wei Hwang, "具自我感知之適應性功率控制系統," TW Patent I349842, Oct. 1, 2011.
    3. Po-Tsang Huang, Wen-Yen Liu and Wei Hwang, "三元內容可定址記憶體漏電流截斷裝置," TW Patent I349288, Oct. 1, 2011.
    4. Yeh-Lin Chu and Wei Hwang, "非同步先進先出暫存器單元," TW Patent I348088, Sep. 1, 2011.

2010

    Journal Papers
    1. Po-Tsang Huang, X.-R. Lee, H.-C. Chang, C.-Y. Li, and Wei Hwang, "A low power DCVSPG pulsed latch for viterbi decoder," Journal of Low Power Electronics, vol. 6, no. 4, Dec. 2010, pp. 551-562.
    Conference Papers

    1. Ming-Hung Chang, Jung-Yi Wu, Wei-Chih Hsieh, Shang-Yuan Lin, You-Wei Liang, and Wei Hwang, "High efficiency power management system for solar energy harvesting applications," IEEE Asia Pacific Conf. Circuits and Systems (APCCAS), Dec. 2010.
    2. Tien-Hung Lin, Po-Tsang Huang, and Wei Hwang, "Power noise suppression technique using active decoupling capacitor for TSV 3D integration," IEEE Int. SoC Conf. (SOCC), Sep. 2010.
    3. Wei Hwang, "Memory-Centric On-Chip Data Communication Platform for Energy-Efficient Heterogenerous Systems," The 10th Emerging Information and Technology (EITC-2010), Stanford University, Palo Alto, CA, USA, Aug. 14-15, 2010.
    4. Po-Tsang Huang and Wei Hwang, "Energy-efficient techniques for circuit design in netowork-on-chip platforms," IEEE Int. Conf. Green Circuits and Systems (ICGCS), Jun. 2010, pp. 305-310.
    5. Hao-I Yang, Ching-Te Chuang, and Wei Hwang, Power-switch gate-oxide breakdown tolerance techniques for power-gated SRAM," IEEE Int. Conf. Integrated Circuit Design and Technology (ICICDT), Jun. 2010, pp. 102-105.
    6. Wei-Chih Hsieh and Wei Hwang, "Low quiescent current multiple output digital controlled voltage regulator," IEEE Int. Symp. Circuits and Systems (ISCAS), May 2010, pp.609-612.
    7. Shi-Wen Chen, Ming-Hung Chang, Wei-Chih Hsieh, and Wei Hwang, "Fully on-chip temperature, process, and voltage sensors," IEEE Int. Symp. Circuits and Systems (ISCAS), May 2010, pp. 897-900.
    8. Yi-Te Chiu, Ming-Hung Chang, Hao-I Yang, and Wei Hwang, "Subthreshold asynchronous FIFO memory for wireless body area networks (WBANs)," Proc. Int. Symp. Medical Information and Communication Technology (ISMICT), Mar. 2010.

     

    United States Patents Granted
    1. Chi-Chen Lai and Wei Hwang, "Pipeline-Based Reconfigurable Mixed-Radix FFT Processor," U.S. Patent 7,849,123, Dec. 7, 2010.
    2. Po-Tsang Huang, Wen-Yen Liu and Wei Hwang, "Leakage Current Cut-off Device for Ternary Content Addressable Memory," U.S. Patent 7,738,275, Jun. 15, 2010.

     

    Taiwan Patents Granted
    1. Shu-Wei Chang, Wei Hwang, and Po-Tsang Huang, "蝴蝶式比較線結構及其搜尋方法," TW Patent I324346, May 1, 2010.
    2. Chi-Chen Lai and Wei Hwang, "管線化架構可重組混合基底的快速傅利葉轉換處理器," TW Patent I323850, Apr. 21, 2010.
    3. Shu-Wei Chang, Ming-Hung Chang, Wei Hwang, and Po-Tsang Huang, "內儲存無關項控制之階層式搜尋線," TW Patent I321793, Mar. 11, 2010.

 

Doctoral Dissertation

  1. Dao-Ping Wang (王道平), "Low Power Multi-Port SRAM design with Write and Read Assist Techniques," (National Chiao Tung University), July 2013
  2. Ming-Hung Chang (張銘宏), "Variation-Aware Ultra-Low Voltage Design for Energy Efficient Chips," (National Chiao Tung University), Jun. 2012
  3. Hao-I Yang (楊皓義), "Robustness of Nano-Scale SRAM Design: Reliablity and Tolerance Techniques," (National Chiao Tung University), Sep. 2011
  4. Wei-Chih Hsieh (謝維致), "Adaptive Power Management Design for 2D and TSV 3DIC Applications," (National Chiao Tung University), Jul. 2011
  5. Po-Tsang Huang (黃柏蒼), "Energy-Efficient Memory-Centric On-Chip Data Communication for Multi-Core SoCs," (National Chiao Tung University), Nov. 2010
  6. B. M. Grossman, "Physics of Submicron MOS Devices," (Columbia University), May 1988.
  7. S. M. So, "Modeling and Photoelectric Characterization of Electrochemically Deposited N-type Cadmium Telluride Thin Film Photovoltaic Devices," (Columbia University), August 1986.
  8. E. Poon, "the Effect of Grain Boundaries on the Carrier Transport in Polycrystalline Silicon," (Columbia University), May 1984.
  9. P. H. Siegel, "Topics in the Optimization of Millimeter-Wave Mixers," (Columbia University), October 1983.
  10. F. Shoucair, "Electrical Characteristics of LSI MOSFET at Very High Temperature," (Columbia University), May 1983.

 

Master Thesis

  1. Chih-Chao Yang (楊傑超) , "Low Power Algorithm-Architecture Co-Design of Fast Independent Component Analysis for Multi-Gas Sensor Applications," 2014.
  2. Chun-Ying Huang (黃?穎), "Energy-Efficient Gas Recognition System with Event-Driven Power Control," 2014.
  3. Tang- Shuan Wang(王唐瑄), "Configurable Discrete Wavelet Transform (DWT) for Multi-Channel Neural Sensing Applications," 2013
  4. Tsu- Ting Chiang(江咨霆), "Thermal Management with In-Situ Process-Temperature Sensor for TSV 3D Integration," 2013
  5. Pei- Chen Wu(吳珮蓁), "PVT-Aware Ultra-Low Voltage Digital Controlled Voltage Regulator Design for Ultra-Low-Power (ULP) DVFS Systems," 2013
  6. Chi-Tuan Chang (張致遠), "Modeling and Memory Management Unit of 3D-Stacked DRAM for 3D High-Definition (HD) Video," 2013
  7. Teng-Chieh Huang (黃騰頡), "Area-Power-Efficient 11-Bit SAR ADC with Delay-Line Enhanceed Turning for Nueral Sensing Applications," 2013
  8. Hon-Jarn Lin (林弘璋), "Low VDDmin 4R4W Multi-Thread Register File Design and Implementation in 40nm CMOS Technology," 2012
  9. Shu-Lin Lai (賴淑琳), "Energy-Efficient TCAM Design for IP Lookup Table in 40nm LP CMOS Process," 2012
  10. Mei-Wei,Chen (陳美維), "Design of Multiphase Clocking and Level Conversion for Ultra-Low-Voltage DVFS System," 2012
  11. Chien-Hen Chen (陳建亨), "Low VDDMIN 512Kb 8T SRAM Design in 40nm CMOS Process," 2011
  12. Po-Jen Yang (楊博任), "Power integrity for TSV 3D integration," 2011
  13. Wei-Hung Du (杜威宏), "Design and Implementation of near-/sub-threshold SRAM-based first-in-first-out (FIFO) memory for WBAN application," 2011
  14. Shang-Yuan Lin (林上圓), "Ultra-low dynamic voltage scaling frequency-ratio-based PVT sensor design and applications," 2011
  15. Yung Chang (張雍), "On-demand memory system for wireless video entertainment systems," 2010
  16. Tien-Hong Lin (林天鴻), "Power integrity in TSV 3D integration," 2010
  17. Chung-Ying Hsieh (謝忠穎), "Ultra-low voltage PVT-robust clock system design for sub/near-threshold green technologies," 2010
  18. Yi-Te Chiu (邱議德), "Ultra-low power sub/near-threshold SRAM deign for dynamic voltage scaling FIFO memory," 2010
  19. Shi-Wen Chen (陳璽文), "near-/sub-threshold PVT sensors for micro-watt DVFS system design," 2010
  20. Shiang-Fei Wang (王湘斐), "Memory-centric on-chip interconnection network for wireless video entertainment systems," 2010
  21. Yi-Ming Chang (張益銘), "An all-digital wide power supply range and wide frequency range DLL-based clock generator," 2009
  22. Shyh-Chyi Yang (楊仕棋), "Design and implementation of low power 8T SRAM and sub-threshold multi-port register file," 2009
  23. Jung-Yi Wu (吳俊毅), "High efficiency power management system for solar energy harvesting applications," 2009
  24. Chih-Hao Kan (闞之皓), "Dynamic frequency scaling clock generator and power efficiency optimization unit for solar cell power management system application," 2008
  25. Tung-Hau Tsai (蔡同豪), "An efficient power management system for solar energy harvesting applications," 2008
  26. Li-Pu Chuang (莊立溥), "An all-digital fast-lock self-calibrated multiphase DLL," 2008
  27. U-Chan Kuo (郭于玄), "Low power timing sharing multithreaded register file," 2008
  28. Mu-Tien Chang (張牧天), "Robust subthreshold SRAM and ultra-low power FIFO memory design," 2008
  29. Wei-Li Fang (方偉立), "Low power and reliable interconnection with self-corrected green coding scheme and self-calibrated voltage scaling technique for network-on-chip," 2008
  30. Yin-Ling Wang (王尹伶), "Ultra low power flip flop design for network-on-chip and viterbi decoder application," 2008
  31. Ssu-Yun Lai (賴思詠), "A robust low power SRAM design with write assist circuits," 2008
  32. Chun-Wen Liu (劉仲文), "Adaptive Voltage Scaling for Discrete Cosine Transformation," 2008
  33. Hsiu-Wen Lin (林秀玟), "A reliable dual supply single gate oxide I/O driver with high voltage tolerant input feature built in a 1.95nm Tox, 65nm CMOS technology," 2007
  34. Wen-Yen Liu (劉文彥), "Low power ternary content addressable memory array and circuit design," 2007
  35. Chi-Chen Lai (賴祈成), "Energy-aware pipeline-based reconfigurable mixed-radix FFT/IFFT processor design," 2006
  36. Chang-Hsuan Chang (張長軒), "A two-layer flexible external memory management for H.264/AVC decoder," 2006
  37. Kwan-Hwa Chen (陳冠華), "Ultra low power area efficient all digital phase-locked loop freqency synthesizer," 2006
  38. Shu-Wei Chang (張書瑋), "Energy-efficient content-addressable memory design for IPv6 adressing lookup application," 2006
  39. Zong-Xi Yang (楊宗熙), "A low power ADPLL-based frequency synthesizer for high speed clock generator," 2006
  40. Jian-Hau Wu (吳健豪), "Dynamic frequency and voltage management design for energy-aware FFT processor application," 2005
  41. Tzu-Chiang Chao (趙自強), "Low power all digital phase-locked loop with built-in jitter self test," 2005
  42. Yeh-Lin Chu (朱燁霖), "Interface circuit design for globally-asynchronous locally-synchronous systems and its application to fast fourier transform architecture," 2005
  43. Chi-Wei Peng (彭奇偉), "Power-gating and XOR-based conditional keepers techniques for energy-efficient content-addressable memory design," 2005
  44. Wei-Keng Chang (張維耿), "Low power pre-comparison content addressable memory and translation lookaside buffer design," 2005
  45. Ching-Yun Cheng (鄭景允), "Gated diode gain cell for low power pseudo SRAM design," 2005
  46. Jen-Wei Yang (楊仁維), "On-chip DC/DC converter with frequency detector and application for reconfigurable multiplier-accumulator unit design," 2005
  47. Min-Sung Tseng (曾銘松), "Time ratio grayscale driving circuits for active matrix organic light emitting diodes," 2005
  48. Tung-Shuan Cheng (鄭東栓), "Dynamic body-biasing and power-gating techniques for low power design," 2004
  49. Shu-Hsuan Lin (林書玄), "High-speed and low power multiplies-accumulator micro-architecture and circuit design," 2004
  50. Chi-Ken Tsai (蔡志侃), "Low power flip-flop and reconfigurable FIFO design," 2004
  51. Chung-Hsien Hua (華重憲), "Low power multi-port register file design for digital signal processors," 2003
  52. J. D. Cressler, "Modeling the Temperature Dependence of DC Conductivity in Heavily Arsenic Doped polycrystalline Silicon, M. Sc. Thesis, (Columbia University), December 1986.
  53. J. Cutro, "Optical and Electrical Properties of Plasma Polymers from Precursor Mixtures of Silane and Phenylsilane," M. Sc. Thesis, (Columbia University), May 1984.
  54. V. Anandu, "A Study of Transversal Filters Using Charge-Coupled Devices," M. Sc. Thesis, (Cocordia University), May 1978.
  55. R. Dikshit, "A GaAs MESFET Mixer for Satellite Communication," (Cocordia University), May 1978.