National Chiao-Tung University

Department of Electronics Engineering & Institute of Electronics





Low Power Flip-Flop and Reconfigable FIFO Desgin






Student : Chi-Ken Tsai

Advisor : Dr. Wei Hwang



Abstract

The clocked storage elements using the low power technique are realized in this paper. The low swing conditional capture edge-triggered flip-flop (LSCCFF) suitable for the low switching activity application is proposed and simulated in TSMC 100nm technology. The single edge-triggered flop-flop uses low swing voltage delay chain, conditional capture technique and stacked technique to reduce the power consumption. A conditional precharged double edge-triggered flip-flop (CPDFF) is presented and simulated in TSMC 100nm technology. The double edge-triggered flip-flop using the conditional precharged technique could be used to reduce half of the clock power in a pipelined system efficiently. In order to reduce the power in the clock tree, a new gating circuit is presented. This gating circuit combines three kinds of the clock gating techniques and could be used to cancel the glitch and reduce the redundant power in the system. The scan-retention mechanism is discussed in the chapter 4. The CPDFF is redesigned with the scan-retention technique and simulated in TSMC 100nm technology. A reconfigurable first-in-first-out register file (FIFO) is proposed and simulated in TSMC 0.13um technology. The FIFO cell could reconfigure the valid storage word length and save 31.7% and 18.3 static power for 16 words and 64 words storage length. This FIFO cell could be applied to the communication systems and used in the memory compiled program.