National Chiao-Tung University

Department of Electronics Engineering & Institute of Electronics





Power-Gating and XOR-Based Conditional Keepers Techniques for Energy-Efficient Content-Addressable Memory Design






Student : Chi-Wei Peng

Advisor : Dr. Wei Hwang



Abstract

The low-power content-addressable memories (CAMs) using power-gating and XOR-based conditional keepers techniques are realized in this thesis. As the technology scale down to deep-submicron and nano-scale eras, the leakage current becomes more serious due to lower threshold voltage and smaller size of transistor devices. Applying power-gating techniques to 64-word x 32-bit CAM is implemented in TSMC 100nm CMOS technology. According to simulation results, the proposed CAM achieves 12% dynamic power reduction and 35% static power consumption and it doesnˇ¦t cause any search time overhead. However, for 64-word x 32-bit CAM array, 7.8% area overhead is caused by power-gating devices.

A novel noise-tolerant match-line scheme which applies the XOR-based conditional keeper techniques is proposed in this thesis. Based on the XOR-gate controller signal, the keeper would be turned off at the beginning of the evaluation phase. Accordingly, the proposed match-line scheme not only saves search power but also reduces the search time. In addition, if the XOR-based conditional keepers are applied, the smaller size of comparison circuit would be required to reduce the match-line loading at the same search time criteria. A 256-word x 128-bit energy-efficient ternary CAM is also proposed and simulations and layout are implemented in TSMC 0.13µ CMOS technology. Simulation results show that 37.8% search time reduction and 15.6% dynamic power saving are achieved by proposed ternary CAM.