National Chiao-Tung University
Department of Electronics Engineering & Institute of Electronics
Gated Diode Gain Cell for Low Power Pseudo SRAM Design
Student : Ching-Yun Cheng
Advisor : Dr. Wei Hwang
The low-power Pseudo SRAM design with 3T1D gain cell and power-gating technique are realized in this thesis. The gated diode acts as a nonlinear capacitance for voltage boosting, where voltage for 1-data is boosted high and voltage for 0-data stays low, achieving significant voltage gain of the internal stored voltage, higher signal margin, higher current drive and low-voltage memory operation. Details about the gated diode structure, its signal amplification, the memory cell circuits and the array structure are presented, followed by comparison to other memory cells. Then 256-word x 32-bit 3T1D gain cell array is implemented in standard logic technology with TSMC 0.13um model for example, applying it to Pseudo-SRAM design. The multi-bank of Pseudo SRAM each has its independent access control circuit, enabling parallel refresh and read-write accesses to different bank. However, 3T1D gain cell is a DRAM cell which needs periodic refresh data for its correct function. Thus one method and apparatus is applied that refresh operation does not interfere with the external accesses under any conditions. In addition, as technology scale down to deep-submicron and nano-scale eras, the leakage current becomes more serious due to lower threshold voltage and smaller size transistor devices. Thus power-gating technique in SA of 3T1D array could reduce 15% standby leakage current during sleep mode and increasing 12% sensing speed during normal mode. But there will be some dynamic power overhead. It is simulated with TSMC 100nm technology model.