National Chiao-Tung University

Department of Electronics Engineering & Institute of Electronics

Low Power All Digital Phase Locked Loop with Built-In Jitter Self Test

Student : Tzu-Chiang Chao

Advisor : Dr. Wei Hwang


A new architecture and algorithm for the all digital phase-locked loop (ADPLL) with low power design is presented in this thesis. By using the new search algorithm, it can accomplish phase lock process within 18 input clock cycles. By using the new architecture, we can combine the functions of the frequency comparator, phase detector and gain generator in one hard block. Also, a new digitally controlled oscillator structure for low power is presented in this thesis and its frequency range is from 200 MHz to 750 MHz. This ADPLL has characteristics of fast frequency locking, small hard cost and lower power consumption.

Clock jitter is one of main issues for PLL and conventionally jitter measurement rely on the external equipment. But the external equipment distort the tested clock signal seriously, it is a good choice to measure jitter by Built-In Jitter Self Test technique. In this thesis, Built-In Jitter Self Test technique is used for jitter measurement.

The proposed ADPLL is simulated and implemented by TSMC 0.13um 1P8M CMOS technology. The supply voltage is 1.2v and total area is 200um x 100um. The simulation results show that when the DCO operates at 560MHz, the jitter is 161.4ps and the total power consumption of ADPLL is 1.7mW.