National Chiao-Tung University

Department of Electronics Engineering & Institute of Electronics





Low Power Pre-Comparison Content Addressable Memory and Translation Lookaside Buffer Design






Student : Wei-Keng Chang

Advisor : Dr. Wei Hwang



Abstract

Using pre-comparison circuit and combining power gating as well as dual vdd for Content-Addressable Memory (CAM) and Translation Lookaside Buffer (TLB) is presented in this thesis. The pre-comparison circuit allows some storing data and searching data for pre-comparison in advance. Through this mechanism, reduce the times of match line discharging. Applying the techniques to 32 words x 32 bits CAM is implemented in TSMC 0.13um CMOS technology. According to simulation results, the pre-comparison CAM achieves 22.8% dynamic power reduction for four pre-comparison bits. The techniques of power gating and dual vdd are applied to pre-comparison CAM and TLB to reduce leakage power. A 32 words x 32 bits pre-comparison CAM and 32 words x 36 bits SRAM are combined for TLB. A TSMC 100nm CMOS technology is used to simulation here. According to simulation results, the pre-comparison CAM can save 31.1% leakage power and TLB can save 33.4% leakage