National Chiao-Tung University

Department of Electronics Engineering & Institute of Electronics





Interface Circuit Design for Globally-Asynchronous Locally-Synchronous Systems and Its Application to Fast Fourier Transform Architecture






Student : Yeh-Lin Chu

Advisor : Dr. Wei Hwang



Abstract

The interface circuit designs using handshake protocols and asynchronous first-in-first-out (FIFO) for globally-asynchronous locally-synchronous (GALS) systems are realized and apply to the Fast Fourier Transform Architecture in this thesis. A new pausible clock controller, write-port and read-port in asynchronous wrappers are proposed and data items can be transferred safely through adjacent wrappers operating at different clock frequencies. To increase the efficiency of throughput at the sender¡¦s module, the asynchronous FIFO is inserted between two adjacent modules. An asynchronous FIFO cell is proposed to reduce the complexity of the handshake circuits by using Muller C element with some modifications. It has the properties of being low power, low latency and reusable. The physical layouts for the FIFO sizes of four, eight and sixteen are implemented based on the TSMC 0.13um 1P8M CMOS technology.

The GALS design combined with dual-supply systems is applied to the 16-point radix-22 single-path delay feedback FFT architecture. The architecture is divided into three wrappers and each wrapper has its own local clock frequency and supply voltage. The interfaces formed from wrappers are implemented by handshake circuits and asynchronous FIFO, which are modified with level converters. Simulation results in TSMC 0.13um technology shows that the 16-point GALS-based FFT architecture in dual supply voltages has 30% power savings and 25.5% latency reduction compared to the globally-synchronous one in single supply voltage. These techniques will be widely used in the future systems-on-a-chip (SOC) design.