National Chiao-Tung University
Department of Electronics Engineering & Institute of Electronics
Energy-Aware Pipeline-based Reconfigurable Mixed-Radix FFT/IFFT Processor Design
Student : Chi-Chen Lai
Advisor : Dr. Wei Hwang
In this thesis, we present a novel FFT/IFFT processor, called reconfigurable mixed-radix (RMR) FFT. It can be easily reconfigured as from 16-point to 4096-point FFT/IFFT with proper mixed-radix algorithm assigned for each mode. The proposed architecture is characterized with scalable energy dissipation for different FFT/IFFT sizes. Unlike general pipeline-based architectures which use a larger internal wordlength to achieve a high signal-to-noise ratio (SNR), our processor keeps the internal wordlength the same as the wordlength of the input data while the block-floating-point (BFP) approach is adopted to maintain the SNR. The pipeline-based architecture with 8-parallel datapath results in low computation cycles.
The simulation result shows that RMR FFT maintain the SNR above 110dB as the FFT size varies. The proposed RMR FFT processor is implemented using TSMC 0.13µm technology with a supply voltage of 1.2V. With the maximum clock rate of 110MHz, the throughput rate can reach 440Msample/s, which is 4 times of the input clock rate. The energy dissipation per FFT ranges from 4.34nJ to 5.115µJ with increasing FFT sizes.