National Chiao-Tung University
Department of Electronics Engineering & Institute of Electronics
A Low Power ADPLL-based Frequency Synthesizer for High Speed Clock Generator
Student : Zong-Xi Yang
Advisor : Dr. Wei Hwang
This thesis proposes a new digital controlled oscillator (DCO) and a new phase frequency detector (PFD) architecture for the all digital phase-locked loop (ADPLL) with low power design. By using the new type digitally controlled delay element (DCDE), a digitally controlled oscillator (DCO) with characteristics of its monotonicity is presented, which makes the DCO design more straightforward. Besides, a new PFD architecture that can finish phase and frequency comparison and adjustment in one reference cycle is also presented.
The proposed ADPLL-based frequency synthesizer has been designed with TSMC 0.13um technology model. It can operate from 300 MHz to 1 GHz, and achieve frequency acquisition within sixteen reference clock cycles (worst case scenario). The peak-to-peak jitter of the output clock is less than 120 ps. Total power dissipation of the ADPLL-based frequency synthesizer is 3.1 mW at 1 GHz with a 1.2 V power supply. With the specification, it could be used for high speed clock generation in high speed DSPs applications.