National Chiao-Tung University

Department of Electronics Engineering & Institute of Electronics

A Robust Low Power SRAM Design with Write Assist Circuits

Student : Ssu-Yun Lai

Advisor : Dr. Wei Hwang


This paper presents a floating BL 8T SRAM Read/Write scheme. A Write assist scheme is also proposed to resolve the serious Write half-select disturb problem, and simulation results show that the proposed Write scheme can work well in more advanced technology nodes, such as 65nm and 45nm. Furthermore, Read/Write replica circuits are designed to control access timing. Moreover, a 32-Kb 8T SRAM subarray is implemented in UMC 90nm CMOS technology. According to simulation results, the proposed 8T SRAM shows its benefits on low power access operations and wide-operating voltage range. It can operate at 1GHz when VDD is 1V and at 200MHz when VDD is 0.5V. So it is suitable to be adopted in portable devices.