National Chiao-Tung University

Department of Electronics Engineering & Institute of Electronics





Low Power Ternary Content Addressable Memory Array and Circuit Design






Student : Wen-Yen Liu

Advisor : Dr. Wei Hwang



Abstract

A new high speed, low-power and noise-tolerant ternary content-addressable memories (TCAMs) using multi-mode data retention power gating technique and super cut-off power-gating technique are proposed in this thesis. These two techniques significantly reduce cell leakage current by taking the advantage of input don't care patterns of IPv6 addressing lookup application. Furthermore, search power is also reduced by applying super cut-off power gating technique under search operation. A 256-word x 144-bit low-power ternary CAM is also proposed. Based on 65nm Berkeley Predictive Technology Model, simulation result shows that 0.23ns search time and 0.047fJ/bit/search energy metric is achieved. Layout implementation using TSMC 0.13µm CMOS technology indicates a 19% area overhead is incurred.