National Chiao-Tung University

Department of Electronics Engineering & Institute of Electronics





Robust Subthreshold SRAM and Ultra-Low Power FIFO Memory Design






Student : Mu-Tien Chang

Advisor : Dr. Wei Hwang



Abstract

Subthreshold SRAM and ultra-low power FIFO memory are indispensable to energy-constrained SoC. The stability of SRAM cell, however, has always been a major challenge to subthreshold SRAM design. This thesis proposes a robust, fully-differential subthreshold 10-transistor SRAM cell with auto-compensation. With the auto-compensation mechanism, the proposed cell exhibits better hold static noise margin (SNM). The cell structure also prevents storage nodes from bitline noise interference, thus improving read SNM. Better write ability is achieved by applying the write-assist technique. Based on UMC 90nm CMOS technology, simulation results show that, at 0.2V supply voltage, the proposed cell has 1.22X hold SNM improvement, 2.09X read SNM improvement, and 2.03X write margin improvement when compared to the conventional 6T SRAM cell.

This thesis, in addition, also proposes a robust, ultra-low power asynchronous FIFO memory. With the self-adaptive power control and the complementary power gating technique, leakage power of the FIFO memory array is minimized. Further, the stability of the FIFO memory is improved under ultra-low supply voltage supply with the proposed dual-VT 7T SRAM cell. Simulation results indicate that the proposed scheme has up to 94% power reduction over conventional designs. In this thesis, the proposed FIFO is implemented in UMC 90nm CMOS technology under 0.5V supply voltage, with 2.21uW power consumption at 5MHz reading frequency and 200kHz writing frequency.