National Chiao-Tung University

Department of Electronics Engineering & Institute of Electronics





Low Power Timing Sharing Multithreaded Register File






Student : U-Chan Kuo

Advisor : Dr. Wei Hwang



Abstract

A low-power multithreaded register file architecture is proposed. Banking architecture and timing sharing access scheme are adopted to reduce the register file area and increase its performance. Floating bitline scheme and divide bitline is also presented to reduce its active power. Furthermore, the register file architecture can be operated at a wide voltage range, and processors would have more strategies to adjust their power/performance. A dual-thread 4W/4R 64x64-bit register file which occupies 426 x 219 µm2 silicon area is implemented in UMC 90nm CMOS technology. Its operating voltage range is between 0.5v and 1.0v. Its active power is around 215.28µW to 197.87µW when operating frequency is 50MHz at 0.5v.