National Chiao-Tung University
Department of Electronics Engineering & Institute of Electronics
Ultra Low Power Flip Flop Design for Network-on-chip and Viterbi Decoder Application
Student : Yin-Ling Wang
Advisor : Dr. Wei Hwang
The clocked storage elements using the low power technique are realized in this paper. The low clock swing edge-triggered flip-flop (LCSFF) suitable for the low switching activity applications is proposed and simulated in UMC 90nm technology, and layout in UMC 90nm standard cell. The single edge-triggered flip-flop uses low swing voltage delay chain generating the operation transparency window for reduces the power consumption. The flip-flop uses the power gating technique to reduce the leakage current.
The low clock swing flip-flop (LCSFF) suitable for the system which used a great quantity of memory. In this thesis it applies to the serializer and deserailizer in network on chip and the survivor memory unit in viterbi decoder. The simulation result shows the applications could save more than 27.5% power.