National Chiao-Tung University

Department of Electronics Engineering & Institute of Electronics





Power Integrity in TSV 3D Integration






Student : Tien-Hong Lin

Advisor : Dr. Wei Hwang



Abstract

Three-dimensional (3D) nanosystems can provide enormous advantages in achieving multi-functional integration, improving system speed and reducing power consumption for future generations of ICs. The robust power delivery system is very important in 3D ICs. In 3D integration, the increasing supply current through both package and through-silicon-via (TSV) would lead to a large simultaneous switching noise potentially. We will introduce basic 3D technology and a proposed design method for placing the TSV bundle in 3D IC under the efficiency condition. Next, the active supply noise regulation scheme is introduced; we propose the power noise suppression technique using active decoupling capacitor (DECAPs) for TSV 3D integration characteristic. Finally, a low quiescent current linear drop regulator (LDO) is proposed to provide difference supply voltage with low noise, and substrate noise canceller is used to suppress the impact of substrate noise. All simulations are based on UMC 65nm CMOS technology and TSV model at 1V supply voltage.